Memory Hierarchy Simulator

Overview

A complete computer memory hierarchy simulator that emulates the full address translation and caching pipeline. From TLB lookups through page table walks to multi-level cache accesses, the simulator processes memory trace files and produces detailed performance statistics — making abstract computer architecture concepts tangible and measurable.

Key Features

• Set-associative TLB with LRU replacement for virtual-to-physical address translation
• Page table simulation with configurable page sizes and virtual/physical addressing modes
• Multi-level cache hierarchy: configurable L1 data cache + optional L2 cache
• Write-through/no-write-allocate policy support
• LRU eviction policy implemented as a generic template across all cache levels
• Trace-driven simulation reading hexadecimal addresses with R/W operations
• Comprehensive statistics: hit/miss ratios, read/write counts per hierarchy level

Architecture

The simulator follows the real hardware access path: TLB → Page Table → L1 Cache → L2 Cache → Main Memory. Address components (tag, index, offset) are extracted via bitwise operations. All structures use configurable set-associative mapping. The simulation processes trace files line-by-line, tracking hits and misses at each level, and generates detailed performance reports.